Electrical Engineering Internship: Uvm Verification
2 maanden geleden
**Introduction**:
Within ASML, the Development & Engineering (D&E) sector is responsible for the specification and the development of ASML products. This assignment is within the Electronic Developmen cluster, responsible for the definition, realization, qualification and integration of electronic functions and modules within these products. In our group we develop printed circuit boards (PCBAs) that often contain a FPGA (Field-Programmable Gate Array) for which HDL (Hardware Description Language) code is developed. This code is referred to as Embedded Logic. Next (and simultanously) to the development itself we want the code (formally) verified using UVM and this will be the topic of your internship. Most projects we work on are for our so-called DUV (Deep Ultra Violet light) systems.
**Your assignment**:
In digital design, AMBA AXI is one of the most popular internal communication protocols. At ASML many FPGA projects are created for Intel/Altera FPGAs and therefore make use of the Avalon protocol. Currently no proper UVM compatible BFM/Verification vendor IP exist for the Avalon protocol making it difficult to use UVM to verify these designs. Fortunately AXI UVM compatible verification IP does exist. Making use of this AXI verification IP, in combination with an AXI4 to Avalon bridge, should make verification of existing Avalon designs possible. But before doing so we need to be sure the AXI4 to Avalon Bridge is working properly.
This assignment will consist of creating a UVM environment to verify whether a AXI4 to Avalon bridge is working properly and therefore can be used in order to verify existing FPGA designs at ASML.
Key deliverables include:
- Come up with a verification strategy.
- Use UVM to verify the AXI4 to Avalon bridge.
- Verify that the Avalon protocol generated by the bridge is properly working. Use coverage (Functional and Code) to prove whether the AXI4 to Avalon bridge is good enough for our needs.
- All code must be stored in a GIT repository.
- Document the test plan, verification architecture and results.
This is a bachelor/master apprentice internship to gain work experience, or a bachelor graduation project (thesis) for 6 months and minimum 4 days per week (of which at least 3 days on-site).
For the interview, you will be asked to prepare a short presentation that you will then present during your interview to the team.
**Your profile**:
To be a match for this internship, you:
- Are a student in Electrical Engineering;
- Have experience with langauages like VHDL and System-Verilog;
- Are motivated and curious;
- Have good communication skills in English (verbal and written).
**Other requirements you need to meet**:
- You are enrolled at an educational institute for the entire duration of the internship;
- You need to be located in the Netherlands to be perform your internship. In case you ‘re currently living/studying outside of the Netherlands, your CV/motivation letter includes the willingness to relocate.
- If you are a non-EU citizen, studying in the Netherlands, your university is willing to sign the documents relevant for doing an internship (i.e., Nuffic agreement).
**Diversity and inclusion**:
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
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