Lead VHDL Design Engineer

2 maanden geleden

Almelo, Overijssel, Nederland Trinamics Beheer B.V. Voltijd
Position Overview

As a Lead VHDL Design Engineer at Trinamics Beheer B.V., you will advance your career in Electrical Engineering. Collaborating within a global team, you will play a crucial role in developing comprehensive (sub-)systems, taking responsibility for the design, implementation, and verification of these systems.

  • You will manage the design, simulation, implementation, and verification of FPGA circuits using VHDL code. Your role will involve collaboration with various disciplines, including hardware and embedded software development.
Requirements
  • A completed Bachelor’s or Master’s degree in Electrical & Electronics Engineering.
  • At least 8 years of experience in VHDL design within product development (Intel, Xilinx, Lattice).
  • Proficient in using simulation tools and measurement equipment for digital circuits, including FPGAs, CPLDs, and standard interfaces such as SPI and I2C.
  • Fluency in English is essential.
Benefits

We offer a competitive salary range (75k-85k) along with exceptional benefits, including:

  • 27 vacation days and 13 ATV days.
  • Holiday allowance.
  • Flexible working hours, enabling you to manage your schedule effectively.
  • Quarterly bonus based on company revenue (up to 5%).

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