Digital IC/RTL Senior Design Engineer

2 weken geleden

Delft, Zuid-Holland, Nederland The Preferred Supplier Voltijd € 100.000 - € 200.000 per jaar


About X

X Corporation
(Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X configurable solutions
offer a rich feature set that enables customers to differentiate their products with high performance, small size,
low power, and high reliability. With over
2 billion devices shipped to date, X is changing the timing industry.

The ASIC Senior Design Engineer will lead
and contribute to circuit design for next-generation products. These products have applications ranging
from high-performance Networking and Communications Infrastructure to ultra-low
power Mobile platforms including wearable devices.

Responsibilities:

·      
Development and verification of
digital block architectures and RTL design for various functions including control state machine, IO
controllers, digital signal processing (DSP), and multiple clock domain
interface management

·      
Work with other digital or
mixed-signal designers to define specifications for digital blocks and interfaces

·      
Analyze architecture, RTL
design for optimal performance, area and power constraints trade- offs

·       Document detailed block and top -level specifications

·      
Perform block level RTL design and verification using
industry leading EDA tools

·       Lead comprehensive design
reviews

·      
Support backend design flow,
including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route,
and netlist verification

·      
Collaborate with analog design
engineers, CAD, systems engineering, test engineering and applications teams to ensure define
optimal DFT, DFM features and achieve rapid silicon bring- up and time to production release

·       Participate in the bring-up of silicon prototypes

·      
Analyze circuit for failure
root cause analysis, investigate anomalous observations in silicon across
various conditions, including PVT
variations, and propose solutions

 
 
 
 
Qualifications & Requirements:

·       M.Sc. or Ph.D. with 5 years of experience in Electrical Engineering

·       Proven track record
at each stage of the following:

·       Digital architecture development and technical feasibility studies

·       Writing detailed block-level specifications and review documents

·      
Detailed design and simulation
of one or more of the following: digital state machines, DSP functions, IO controllers, multiple block
interface management including multi-clock domain designs, microcontroller design
and implementation, memory and register file controllers

·       Proficiency with EDA tools and design languages including Verilog, VHDL, SystemVerilog

·       Extensive experience in digital
block verification strategies

·      
Understanding of digital design
flow from architecture design to sign-off

·       Experience with DSP concepts, circuits, architectures, and implementation

·      
Ability to communicate and work
effectively with geographically dispersed teams of mixed- signal,
digital, layout, and verifications
engineers

·       Ability to work independently and drive solutions to challenging problems

·      
Good understanding of modeling
signal processing algorithm using Matlab or Simulink

·       Experience in performing synthesis, static timing
analysis, and netlist
verifications

·      
Understanding of digital backend
flow for Place & Route (PNR)

·       Experience in digital DFT flow (stuck-at / TDF scan insertion and ATPG)

·      
Experience in complex finite
state machine design

Desired Characteristics & Attributes:

·       Passionate, self-starter with strong commitment to flawless execution

·       Excellent written and verbal
communication skills required

·      
Ability to work well with others in a fast-paced collaborative team environment


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