Senior VHDL Design Engineer

6 maanden geleden

Almelo, Nederland Trinamics Beheer B.V. Voltijd
Functieomschrijving

As a Senior VHDL Design Engineerwith Benchmark, you'll grow in Electrical Engineering. In a globalteam, you contribute to building complete (sub-)systems, takingcharge of designing, implementing, and verifying thesesystems.

  • You oversee thedesign, simulation, implementation, and verification of FPGAcircuits, employing VHDL code. Your collaboration extends to otherdisciplines, including hardware and embedded softwaredevelopment.

Functie-eisen
  • Completed Bacheloror Master in Electrical & ElectronicsEngineering.
  • Minimum of 8 years of experience inVHDL design within product development (Intel, Xilinx,Lattice)
  • You bringexperience in utilizing simulation tools and measurement equipmentfor digital circuits, including FPGAs, CPLDs, and standardinterfaces like SPI andI2C.
  • Fluent inEnglish

Arbeidsvoorwaarden

In addition to a competitive salary(75k-85k), we provide outstanding benefits suchas:

  • 27 vacation days and 13 ATVdays.
  • Holidayallowance
  • Flexible working hours, allowingyou to arrange your schedule, ensuring completion of yourwork.
  • Quarterly bonus based on revenue(up to 5%)

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