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Senior VHDL Design Engineer
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VHDL Design Lead
2 maanden geleden
About the Role
As a Senior VHDL Design Engineer at Trinamics Beheer B.V., you will be part of a global team responsible for designing, implementing, and verifying complex electronic systems. Your expertise in VHDL design will be instrumental in creating innovative solutions for our clients.
Key Responsibilities
- Lead the design, simulation, implementation, and verification of FPGA circuits using VHDL code.
- Collaborate with cross-functional teams, including hardware and embedded software development, to ensure seamless system integration.
- Develop and maintain high-quality VHDL code, adhering to industry standards and best practices.
- Contribute to the development of technical documentation, including design specifications and test plans.
Requirements
- Bachelor or Master's degree in Electrical & Electronics Engineering.
- Minimum 8 years of experience in VHDL design within product development, with expertise in utilizing simulation tools and measurement equipment for digital circuits.
- Experience with FPGAs, CPLDs, and standard interfaces like SPI and I2C.
- Fluent in English.
What We Offer
- Competitive salary (75k-85k) and outstanding benefits package.
- 27 vacation days and 13 ATV days.
- Holiday allowance.
- Flexible working hours, allowing you to arrange your schedule, ensuring completion of your work.
- Quarterly bonus based on revenue (up to 5%).