Senior Digital Design Engineer

4 weken geleden


Rijswijk, Zuid-Holland, Nederland SiTime Voltijd
About SiTime

SiTime Corporation is a leading provider of precision timing solutions. Our innovative MEMS-based timing products offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.

Job Summary

We are seeking a highly skilled Senior Logic Design Engineer to join our team. As a key member of our digital design team, you will be responsible for developing micro-architecture specifications, designing digital logic circuits, and verifying system-level functionality.

Responsibilities:
  • Develop micro-architecture specifications of the logic circuit from reading and comprehending the Product Requirement Document (PRD)
  • Develop the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL
  • Develop standalone test benches to verify the RTL behavior
  • Write and verify SystemVerilog Assertions (SVA) for a design
  • Write timing constraints and clock definition for synthesis and place and route tools
  • Run industry-standard synthesis tools (e.g., Genus or Design Compiler) and be able to fix timing problems if they arise
  • Understand various design tradeoffs including timing/area/power and know how to improve them
  • Read and understand the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time)
  • Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams
  • Post-Si bring-up, validation, and debugging
Qualifications & Requirements:
  • Master's degree in electrical engineering plus 5 years of relevant work experience in the industry
  • Excellent verbal and written communication skills in English
  • Proficient in Verilog and SystemVerilog
  • Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc
  • Experience in designing mixed-signal digital logic
  • Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design
  • Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA
  • Skilled in scripting languages Perl/Tcl/Python
Desired Characteristics & Attributes:
  • Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience
  • 2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing
  • 2-5 years of experience in designing Digital Phase-Locked Loops (DPLL)
  • Experience in complex FSM design
  • Familiarity with MATLAB, Simulink, or any other high-level modeling tools
  • Experience in low-power digital design flow
  • Basic understanding of the Control Theory

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